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1. |
An error detecting and correcting coding method for bilevel images of line drawings using the redundancy of the images |
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Systems and Computers in Japan,
Volume 18,
Issue 1,
1987,
Page 1-12
Michihiko Minoh,
Toshiyuki Sakai,
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摘要:
AbstractThe development of technology concerning semiconductors and optical fibers now makes image transmission cheaper and more practical. This paper describes an error correcting coding method for binary images of line drawings. First the bilevel images of line drawings are represented by legal patterns, which are defined with a 3 × 3‐pixel unit mesh (window) and employ line constraints. The resulting image is a picture represented by a legal symbol connection (LSC‐picture). This picture includes certain connecting relations among the neighboring legal patterns, which are considered to represent explicitly the redundancy of the original image. Next we encode the picture using a legal pattern as a coding unit. The information source model used for encoding is a simple Markov model. We use line‐to‐line dependencies for the purpose of error detection and correction. When a transmission error is detected by checking the relations, the decoding process generates a tree called an “error correcting tree.” The problem of correcting the transmission error is considered as one of how to search the error correcting tree. The simulation results of this method show that almost all the transmission errors can be corrected if we incorporate a little redundancy of the code words themselves, as in an ordinary method. At the same time, the compression ratio is as high as that of the MR coding method. For image transmission in the future we believe that a description should be considered which can make explicit the redundancy of the image itself as much as possible and that the redundancy should be utilized not only for compressing the amount of data but also for correcting transmi
ISSN:0882-1666
DOI:10.1002/scj.4690180101
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1987
数据来源: WILEY
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2. |
Method of pattern positioning for automatic verification of seal imprint |
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Systems and Computers in Japan,
Volume 18,
Issue 1,
1987,
Page 13-22
Katsuhiko Ueda,
Yoshikazu Nakamura,
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摘要:
AbstractIn automatic computer verification of seal imprints accurate positioning of an examined seal imprint over a registered imprint is of great importance. This paper proposes a method which positions an examined seal imprint in relation to a parallel shift and rotation by using the centroid of its frame figure and the pixels on a circle of a certain radius from the centroid. Since this method achieves positioning by using local features of the examined seal imprint, rapid positioning is possible. In the presence of small defects in the imprint frame this method has the advantage that the centroid of the seal imprint is accurately obtained and is not affected by distortion of the imprint frame. In a positioning experiment based on this method 240 actual seal imprints were used. All imprints were positioned within a ±0.1‐mm parallel shift error and more than 99% of the seal imprints were positioned within ±1.76° rotation angle errors. A verification experiment was conducted using a seal imprint verification system which incorporated the principles of this method. As a result, the verification error which was caused by the positioning error was found to be 0.83%. The experimental results show that the proposed positioning method is efficient for automatic verification of seal impr
ISSN:0882-1666
DOI:10.1002/scj.4690180102
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1987
数据来源: WILEY
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3. |
Decoding method for shortened fire codes and its application to VLSI processor |
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Systems and Computers in Japan,
Volume 18,
Issue 1,
1987,
Page 23-32
Kazuhiko Iwasaki,
Tsuneo Funabashi,
Tatsuaki Ueno,
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摘要:
AbstractThe disc system is one of the areas of applications for the error‐correcting code. For this purpose, a Fire code with the generating polynomialG(x) = (xc+ 1) ×p(x) is frequently used. This paper considers the shortened Fire code, where the length of the code can be reduced according to the length of the record used. A decoding method suitable for VLSI is proposed. It is noted that the content of the feedback shift register withp(x) as the divider returns to the original pattern when it is shifted by the periodeofp(x), and the speed is improved by ignoring the integer multiple shifts ofe. This decoding method requires less hardware (i. e., shift registers and counters), and has the merits of easiness in design and expandability, according to the record length. The principle is expanded to the general cyclic code. The proposed decoding method is implemented on the hard disc controller (peripheral LSI for HDC 16 bit microcomputers). A 32‐bit Fire code is used. For a typical record length of 512 bits in the disc system, the speed was comparable to that of the high‐speed decoding. The error‐correcting part is composed of 6700 Tr, which is 5.2% of the whole system (129 kTr). This figure demonstrates the practical usefulness of the proposed method in VLS
ISSN:0882-1666
DOI:10.1002/scj.4690180103
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1987
数据来源: WILEY
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4. |
The application of tense logic to database behavioral description |
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Systems and Computers in Japan,
Volume 18,
Issue 1,
1987,
Page 33-41
Koichiro Tarabe,
Atuyuki Suzuki,
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摘要:
AbstractThis paper defines a presupposition‐free many‐sorted tense theory MQRT*=. This theory is applied to behavior description of historical database. Using this theory makes it possible to express clearly not only the usual schema information but also such behavioral aspects of schema as event, dynamic integrity constraint, etc. This is the first time behavior description has been provided by a complete theory. This theory is also applied to schema description of historical database. Providing both schema description and behavior description amounts to total, full description of historical datab
ISSN:0882-1666
DOI:10.1002/scj.4690180104
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1987
数据来源: WILEY
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5. |
Realization method of totally shelf—Checking error checking and correcting circuits for main memory systems |
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Systems and Computers in Japan,
Volume 18,
Issue 1,
1987,
Page 42-54
Shuichi Shinmori,
Masaaki Hoda,
Yoshiaki Koga,
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摘要:
AbstractThis paper proposes a realization method for totally self‐checking ECC (Error Correcting and Checking) circuits using SEC‐DED (Single‐Error‐Correcting and Double‐Errors‐Detecting) codes. The methods of constructing self‐checking ECC circuits are divided into two categories: the method of constructing them as a whole; and the method of adding a redundant circuit for each functional circuit. Up to now, the former conventional method has had such problems as the number of gates being too large and the fault‐detectability being insufficient. These problems can be solved by adding one checker circuit for the ECC circuits in this paper. First, we design the new odd‐weight‐columnH‐matrix which has the ability of SEC‐DED codes. Then the syndrome generator, the syndrome decoder, and one parity tree checker circuit are constructed based on thisH‐matrix. Furthermore, this proposed method can distinguish a stuck‐at fault in ECC circuits from errors in the main memory. The increasing rate of gates to realize totally self‐checking ECC circuits is about 37 to 56% for the information‐bit lengthk= 16‐64 bits. This is smaller by about 5% than the best method of adding redundant ci
ISSN:0882-1666
DOI:10.1002/scj.4690180105
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1987
数据来源: WILEY
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6. |
Load scheduling schemes using inter—PE network |
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Systems and Computers in Japan,
Volume 18,
Issue 1,
1987,
Page 55-66
Kei Hiraki,
Satoshi Sekiguchi,
Toshio Shimada,
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摘要:
AbstractThe load distribution among processing elements (PE) in the parallel computer system is one of the major factors affecting the performance of the entire system. This paper discusses the dynamic distribution scheme which distributes the load at the execution of the task. The major factor, which affects the performance in the dynamic load distribution scheme, is the information concerning the loading situation of each PE and the data transfer for distributing the load. This paper proposes a dynamic load distribution scheme, which reduces these overheads considerably by utilizing the network. The idea can be applied to both the circuit‐switching network and the packet‐switching network. Especially, the scheme based on the packet‐switching network is one of the load distribution schemes suited to the instruction‐level data‐driven computer, using the packet as the major communication means among PE's. Based on the proposal of the scheme, the performance of the system is evaluated for a typical configuration example for the parallel processing program. It is verified as a result that the proposed system operates very closely to the ideal dynamic load distributi
ISSN:0882-1666
DOI:10.1002/scj.4690180106
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1987
数据来源: WILEY
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7. |
A fast image filtering processor using the fermat number transform |
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Systems and Computers in Japan,
Volume 18,
Issue 1,
1987,
Page 67-78
Nobumoto Yamane,
Yoshitaka Morikawa,
Hiroshi Hamada,
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摘要:
AbstractThis paper discusses a newly developed high‐speed image filtering processor, aiming at high‐accuracy and high‐speed isotropic filtering. The isotropic filtering is made efficient by the following features.(1) The image is sampled over the triangular lattice and processed by the hexagonal finite‐impulse response (FIR) filter. (2) The filter is realized by the Fermat number transform (FNT) with hexagonal sectioning procedure.The high‐speed hardware has the following features: (1) FNT‐butterfly circuit using 3‐input adders; and (2) multiple processing by the memory structure with three‐level hierarchies. By those features, the proposed system executes the filtering in approximately 0.5 s for an image composed of 512 × 512 pixels in triangular lattice (512 × 591 pixels in square lattice) by a hexagonal FIR filter with edge distance of 15 (17 × 17 in square lattice‐square FIR filter). This paper describes the features, architecture and operation of the proposed system. Then the result of correcting the isotropic blur is presented, indicating that a practically sufficient
ISSN:0882-1666
DOI:10.1002/scj.4690180107
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1987
数据来源: WILEY
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8. |
Defect detection method for stamped patterns utilizing random access parallel matching technique |
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Systems and Computers in Japan,
Volume 18,
Issue 1,
1987,
Page 79-90
Yoshihiro Shima,
Seiji Kashioka,
Toshikazu Yasue,
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摘要:
AbstractIn the fabrication processor of electronic components, the outlook inspection has been performed primarily by visual observation. The automation of this process is presently considered important. This paper describes automatic defect detection considering the stamped pattern on the surface of the electronic parts on the integrated circuit, etc. The only clue to the information on the kind of electronics part is the characters and symbols stamped on its surface. In this sense, the stamped pattern is considered as a part of the part quality. Some defects of the stamped pattern are the disappearance, lack of a part, and dirt. The feature of these defects are discussed first. The fixed‐point sampling is considered which detects the existence of the character pattern at the observation point. The method is modified so that the decision can be made at the observation point along the stroke. Furthermore, a character defect detection system is proposed which can shift the observation point in horizontal and vertical directions so that the system can cope with the variation of the position of the character. A dedicated image processing device was developed to perform the defect detection with high speed. The architecture and the operation of the system are described. The system is advantageous in that the high‐speed operation is realized by the pipeline control for a series of processings, from the parallel read‐out of the local patterns in the image memory to the matching operation. Finally, the configuration of the experimental system is described and the results are shown for the automatic outlook inspection for the stamped pattern of the actual electronic part, thereby indicating the usefulness of the proposed s
ISSN:0882-1666
DOI:10.1002/scj.4690180108
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1987
数据来源: WILEY
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9. |
Analysis of memory fan effect by paired association |
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Systems and Computers in Japan,
Volume 18,
Issue 1,
1987,
Page 91-101
Yuzo Hirai,
Kenji Hiwatashi,
Tomoko Kikuchi,
Ken‐Ichi Kamijo,
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摘要:
AbstractThree kinds of psychological experiments were performed by a paired‐association paradigm in order to investigate the properties of human memory. The experiments are based on the fan effect where a longer time is required for retrieval with the increase of the number of items associated with an item. In the first experiment, the association pair of meaningless items is used as the object of memory and the retrieval time is measured for the cued recall and recognition tasks. It is seen that while the fan effect is produced in the recognition task, it is not produced in the cued call recall task. In the second experiment, the seman‐tically related association pair (noun‐verb and noun‐noun) is used and the retrieval time is measured in the same way as in experiment 1. As a result it is seen that the fan effect is produced in both recognition and cued recall tasks. The obtained results seem to suggest that a difference exists in the memory structure for the meaningless and semantically related items. It is also suggested that there is a difference in the memory strategy based on the meanings. In the third experiment, the association pair is used where a verb and a noun are associated with the same noun. As a result of the cued recall task, it is shown that the verb is easier to be recalled than the noun. This will be accounted for by assuming that a kind of case structure exists in the
ISSN:0882-1666
DOI:10.1002/scj.4690180109
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1987
数据来源: WILEY
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10. |
A neural network model for the mechanism of selective attention in visual pattern recognition |
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Systems and Computers in Japan,
Volume 18,
Issue 1,
1987,
Page 102-113
Kunihiko Fukushima,
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摘要:
AbstractWhen a complex figure consisting of two or more patterns is presented, we, as human beings, can selectively concentrate on these patterns one at a time, and recognize individual patterns in turn. At the same time, we can separate a component of the pattern being recognized, and extract it from the rest of the figure. Even if one of the patterns on which we are concentrating contains noise or defects, we can recall a complete pattern from which the noise and the defects have been eliminated. It is not necessary for perfect recall that the stimulus pattern be identical in shape to the pattern which we learned. Even though the pattern is distorted in shape or changed in size, we can recognize it and eliminate defects by interpolation. During the process of interpolation, we make full use of even slight traces in the defective parts of the pattern on which we are selectively concentrating, and recall the perfect original pattern. A model which performs this function of the human brain, that is, of the function of the selective concentration in visual pattern recognition, is proposed, and its behavior is demonstrated by computer simulation. The model consists of a hierarchical neural network which has efferent connections between cells.
ISSN:0882-1666
DOI:10.1002/scj.4690180110
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1987
数据来源: WILEY
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