摘要:

AbstractThis paper discusses a CMOS row decoder, which is indispensable to a VLSI DRAM. The factors involved in operational delay are analyzed and an investigation is done in order to be able to realize high‐speed operation, while maintaining the feature of low power consumption. The following structure was decided upon in order to achieve highspeed operation: the NAND gate of the CMOS row decoder is shared by more than one of the subdecoders. The size of the MOS transistors (MOST) which make up the gate is increased. In the size‐ratio of the p‐ and n‐channel MOSTs in the CMOS inverter of the next stage, the p‐channel MOST is made larger than in the usual design. A problem which arises from the unbalanced CMOS inverter is pointed out, and the optimization of the pre‐charge signal of the decoder is discussed in order to deal with this problem.For comparison, the optimized decoder circuit and an NMOS decoder are built into a IM DRAM test device, and their performances are compared. As a result of this test, it was verified that the operating current of the proposed CMOS row decoder is roughly 8 mA smaller than that of the NMOS circuit. The operational delay is negligible. By adopting the optimal precharge signal, a decoder circuit with a wide operational margin

ISSN:8756-663X    

DOI:10.1002/ecjb.4420730301

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1990

数据来源: WILEY

摘要:

AbstractHigh integration density and high‐speed operation are obtainable by miniaturization of bipolar LSI devices. In modern bipolar integrated transistors, an undesired current flows into the substrate due to the parasitic sub‐PNP transistor. For example, for Bi‐CMOS circuits, this substrate current can be the main cause of reduction in the supply voltage.This paper proposes merged models for the NPN and lateral PNP transistors which include the substrate current due to the parasitic sub‐PNP transistor. The extraction of model parameters for the calculation of substrate current is also described. By the application of these models to the simulation of NPN transistor for Bi‐CMOS memory and lateral PNP transistor of linear process, good accuracy of dc saturation and substrate current characteristics can be obtained. Its application to the simulation of decoder/memory cell of Bi‐CMOS memory is d

ISSN:8756-663X    

DOI:10.1002/ecjb.4420730302

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1990

数据来源: WILEY

摘要:

AbstractIn a piezoelectric resonator supported by a thin film with an air gap between the substrate and the resonator, it is difficult to construct a resonator because of the stress in the resonator. Stress also affects the electrical properties in this device. In this study, stress is minimized by using (1) a structure supported at one end, and (2) a surface‐supported structure. Piezoelectric resonators supported by a thin film with an easily constructed structure were proposed. In device (1), the resonant frequency, the quality factorQand the capacitance ratio γ were 300 MHz, 1200 and 54, respectively. In device (2), the resonant frequency,Qand γ were 1.77 GHz, 300 and 250, respectively. Breakage of the thin film with a small air gap and stress in the film will be discussed. Finally, the usefulness of this method will be pro

ISSN:8756-663X    

DOI:10.1002/ecjb.4420730303

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1990

数据来源: WILEY

摘要:

AbstractThis paper describes the present and future status of silicon crystal technology for high‐performance silicon VLSI. For 4 M to 16 M memory IC's, conventional technology must be developed further and the crystalline quality by gettering and wafer shape must be improved. The development of BiCMOS technology depends strongly on the improvement of epitaxial growth technology. A reduction in the device size causes problems in reliability and in the physical limit of the device performance.To overcome these problems, research and development of new crystal growth technologies are in demand. Among these technologies, the SOI (silicon on insulator) technology, selective epitaxial growth and molecular beam epitaxy will be the key technologies for high‐performance VLSI with ultrahigh speed, very large‐scale and ultramultifunc

ISSN:8756-663X    

DOI:10.1002/ecjb.4420730304

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1990

数据来源: WILEY

摘要:

AbstractRecently, many types of very high‐speed static RAMs (SRAM) using CMOS or BiCMOS technologies have been announced. Even with CMOS SRAMs, which operate in the range of 10 ns access time, both device and circuit technologies and also usage and reliability problems become prominent, and must be solved in order to achieve adequate speed performance.This paper discusses technical problems and their realistic solutions for achieving very‐high speed SRAMs using CMOS from the viewpoint of device and circuit technologies. Consequently, short channel MOSFETs using 1.0 μm NMOS and 1.0 μm PMOS gate lengths were used to reduce the access time. In order to reduce the soft‐errors that cause problems when high‐speed SRAMs are operated with a short cycle time, theVthof memory cell transistors is set higher than the level in the other circuits. Hence, the soft‐error rate is the same when the device is operated with a longer cycle time.With respect to circuit technology, a high sensitivity sense amplifier is used with a smaller gain decrease under low voltage, a circumstance which is suitable to high‐speed SRAMs that are sensitive to supply voltage bounce due to electrical noise within the chip.In order to implement systems using high‐speed SRAMs, a write‐timing control circuit is introduced, which alleviates the timing constraints on the address skew during write timing. Utilizing these technologies with a CMOS process, a 256‐K SRAM with an access time of 13 n

ISSN:8756-663X    

DOI:10.1002/ecjb.4420730305

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1990

数据来源: WILEY

摘要:

AbstractIn the substrate current characteristics and the drain current characteristics in a submicron nMOSFET with an LDD structure, the problem of asymmetry caused by ion implantation occurs if the measurement is done with the source and drain interchanged. It is found also that significant asymmetry appears in the subthreshold current characteristics (threshold voltage) in a submicron pMOSFET with EPS (efficient punchthrough stops). By introducing the four‐step implantation method as a technique to form LDD and EPS regions, an attempt was made to improve asymmetry. By this method, symmetric electrical characteristics are obtained without changing the conventional process and without reducing the throughput. Further, the unbalance of the threshold voltages between the pair transistors was measured because they have the greatest effect on the sensitivity of the sense amplifier important in the VLSIDRAM. It was found that the four‐step implantation method is extremely effective for suppressing the asymmetry without changing the circuit des

ISSN:8756-663X    

DOI:10.1002/ecjb.4420730306

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1990

数据来源: WILEY

摘要:

AbstractThis paper describes the crystallinity, electric properties and bandgap of Si films deposited on a single‐crystalline substrate by plasma CVD, and the application of this film to the heteroemitter of an Si‐HBT.The plasma CVD Si film is grown epitaxially near the interface with a single‐crystalline substrate (in this experiment, the thickness was less than 10 nm). However, as the film thickness increases, the crystallinity of the film degrades and the film eventually becomes μc‐Si. The crystallinity depends on the surface orientation of the substrate. The epitaxial growth occurs more easily on a (100) surface than on a (111) surface. The film resistivity is dependent on the degree of the epitaxy and is lower in a film grown on a (100) substrate than on a (111) substrate, and lower near the interface than the surface.The bandgap estimated from the optical absorption characteristic is 1.34 eV. This value is smaller than that of a film deposited on a glass substrate but is larger than that of single‐crystalline Si. Therefore, it is expected that this film can be used to form a wide bandgap heteroemitter structure. In the Si‐HBT formed by using this film for the emitter, the current gain was as high as 480. When a polycrystalline film was used, the current gain was only 15. Therefore, the high current gain of a μc‐Si heteroemitter transistor is not due to the oxide layer at the interface but to the wide bandga

ISSN:8756-663X    

DOI:10.1002/ecjb.4420730307

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1990

数据来源: WILEY

摘要:

AbstractA new self‐alignment process technology SATURN (self alignment technology utilizing reserved nitride) has been developed in which the selective oxidation of polysilicon and the nitride films in this oxidation process are used for a number of objectives with a view to improve the operating speed of the bipolar devices. This method is characterized by the control of the emitter stripe width by the side wall spacer film thickness and the control of the distance between the emitter and the external base by the selective oxide film thickness are carried out independently. A process of optimization based on the forementioned control was carried out so that the small transistor with an emitter stripe width of 0.5 μm and a distance of 0.35 μm between the emitter contact and the base contact was realized. This resulted in a current gain of 66 and a cutoff frequency of 12 GHz. Further, this transistor was applied in the ECL circuit which resulted in the performance with the minimum propagation delay time of 88 ps in an inverter gate and the maximum dividing frequency of 3.5 GHz in a 1/8 divi

ISSN:8756-663X    

DOI:10.1002/ecjb.4420730308

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1990

数据来源: WILEY

摘要:

AbstractFor realization of ultrahigh‐speed LSIs, devices with large current driving capabilities and interconnects with small parasitic resistances and small parasitic capacitances are desired. When a high‐speed signal propagates along the conventional metal‐insulator semiconductor (MIS) interconnect, the signal is subject to waveform distortion due to the power consumption by the current induced in an Si substrate. On the other hand, an interconnect‐ground capacitance with a certain magnitude is required for suppression of cross talk. For these reasons, an interconnect of the metal‐oxide‐metal structure is proposed.Next, in regard to devices, it is considered that the MOS transistor is an induced charge control device and hence the speed increase can be accomplished with superposition of the potential control function of the bipolar transistor. This objective is accomplished in the current overshoot transistor in which the floating potential of the channel formation region of the SOIMOSFET is used intentionally. If the base width of the bipolar transistor is made extremely small, the carrier velocity is saturated so that the current value becomes independent of the base width. In addition, the difference between the uniform base and the graded base disappears. In the ultra‐high‐speed LSIs, the load to the interconnect increases due to the cross‐talk suppression. Therefore, the importance of these devices with large current driving capabilities becomes even

ISSN:8756-663X    

DOI:10.1002/ecjb.4420730309

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1990

数据来源: WILEY

摘要:

AbstractSoliton is one of the key concepts that will support future optical communications with a capability for large‐capacity, longdistance transmission systems. In general, the propagation of soliton pulses in an optical fiber is described by the perturbed nonlinear Schrödinger equation (PNLSE). Without any perturbation, this equation is reduced to the canonical nonlinear Schrödinger equation (NLSE) and can be solved analytically. However, in an attempt to take into account a variety of perturbations such as higher‐order dispersion, nonlinear dispersion, shock effect, induced Raman scattering, dissipation, etc., it is no longer solvable in an analytical fashion.This paper proposes a useful method based on the finite‐element method to carry out systematically the evolutional analysis that includes these perturbations. This method can easily deal with cases with realistic perturbations. To confirm the validity of this approach, it is applied to solving unperturbed cases, and it is shown that the same results as those using other solution methods are o

ISSN:8756-663X    

DOI:10.1002/ecjb.4420730310

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1990

数据来源: WILEY