1. |
Voltage-controlled negative resistance inp+-i-n+planar diodes with injection gate |
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IEE Proceedings I (Solid-State and Electron Devices),
Volume 133,
Issue 1,
1986,
Page 1-5
S.Supadech,
S.Okazaki,
Y.Akiba,
T.Kurosu,
M.Lida,
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摘要:
The electrical properties of Sip+-i-n+diodes with a hole injecting gate are studied. The gate is placed between the anode (p+) and the cathode (n+). Under appropriate conditions of both the gate location and the positive gate voltage with respect to the cathode, these devices exhibit voltage-controlled negative resistance (VCNR). A phenomenological model for the occurrence of VCNR is proposed. The model considers the interaction between twop+-i-n+diodes fabricated in the same substrate. Electrical characteristics are analysed on the basis of this model. The experimental results can be understood phenomenologically using the above model.
DOI:10.1049/ip-i-1.1986.0001
出版商:IEE
年代:1986
数据来源: IET
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2. |
Analysis of optical writing mode in solid-state imaging devices with inherent MNOS memory |
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IEE Proceedings I (Solid-State and Electron Devices),
Volume 133,
Issue 1,
1986,
Page 6-12
T.Ando,
H.Yamasaki,
T.Sugishita,
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PDF (714KB)
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摘要:
A model for optical writing in solid-state imaging devices with an inherent MNOS memory is presented. It is shown that writing under low light levels is highly enhanced by the use of a proper bias-charge (fat-zero). The optimum operating condition under which wide dynamic range can be realised without degradation of the writing is also derived. Experimental results from test elements support these theoretical predictions. Finally, erase characteristics of the MNOS analog memory are presented.
DOI:10.1049/ip-i-1.1986.0002
出版商:IEE
年代:1986
数据来源: IET
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3. |
Taper etching of the thermal oxide layer |
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IEE Proceedings I (Solid-State and Electron Devices),
Volume 133,
Issue 1,
1986,
Page 13-17
Y.I.Choi,
C.K.Kim,
Y.S.Kwon,
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PDF (632KB)
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摘要:
Controllable taper windows in thermally grown silicon dioxide layers are produced by depositing a thin layer of silicafilm on the thermal oxide layer before chemical etching. As the densification temperature of silicafilm is varied from 175°C to 1150°C, taper angles from 3° to 40° are obtained. Fermat' s principle of least time is employed to derive the expression for the etched profiles of the oxide layer.
DOI:10.1049/ip-i-1.1986.0003
出版商:IEE
年代:1986
数据来源: IET
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4. |
Stability of Schottky barriers at high temperatures for use in GaAs MESFET technology |
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IEE Proceedings I (Solid-State and Electron Devices),
Volume 133,
Issue 1,
1986,
Page 18-24
D.A.Allan,
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摘要:
The stability of Schottky barrier gates in GaAs MESFETS has been investigated to allow device processing at elevated temperatures. The incorporation of a Pt diffusion barrier into the TiAu structure gives stability of electrical characteristics up to 350°C and a Ti-W-Au contact is stable up to 400°C. To achieve higher temperature stability for use in a self aligned gate (SAG) technology, a more stable Schottky barrier material such as a TiW (30 at % Ti) alloy has been used. This has been found to be unreliable above 750°C and it has been found necessary to use a tungsten silicide contact W1.6Si (37 at % Si) to achieve reproducible Schottky contacts at the temperature used for ion implantation activation (800°C). SAGFETs have been fabricated using W1.6Si and initial results indicate good yields (91%), highgm(190 mS/mm) and good uniformity (standard deviation = 6.8% for 293 devices).
DOI:10.1049/ip-i-1.1986.0004
出版商:IEE
年代:1986
数据来源: IET
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5. |
Elimination of surface current induced failure in millimetre wave Baritt diodes |
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IEE Proceedings I (Solid-State and Electron Devices),
Volume 133,
Issue 1,
1986,
Page 25-27
J.Freyer,
U.Guettich,
M.Claassen,
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PDF (361KB)
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摘要:
The influence of surface charges on the current/voltage characteristics of Baritt diodes is described and an improved Baritt diode geometry avoiding surface currents is suggested which leads to sharpI/Vbehaviour and hence to stable oscillation conditions.
DOI:10.1049/ip-i-1.1986.0005
出版商:IEE
年代:1986
数据来源: IET
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