摘要:

Examination of the total effective word line capacitance loading a DRAM word line driver reveals a dynamic effect which changes the capacitance relative to static computations. The magnitude of the ‘dynamic’ capacitance can be significant when the rates of change of the storage node and word line voltage waveforms are comparable. The source of this effect is shown to be charge transfer between storage nodes and bit lines during the activation of the word line. Implications of the dynamic effect for word line design and boosting in the 1/2 VDD sensing scheme are discussed. The effect occurs for any sensing scheme; it represents another variable affecting overall sensing performance in dynamic RAM.

DOI:10.1049/ip-i-1.1988.0001

出版商:IEE    

年代:1988

数据来源: IET

摘要:

Computer simulation under static conditions is performed to compare gain and saturation voltage with collector current for a power switching transistor for which process data had been measured. The transistor simulation is then carried out for a range of static solutions to generate look-up tables forming the circuit CAD model. A circuit analysis program is then used to examine the variation of current density with time within the transistor. Comparing instantaneous current density and collector-emitter voltage with a static solution of the ionisation integral under high current density conditions allows prediction of second breakdown under reverse base drive with inductive load. Computer results are compared with measured data.

DOI:10.1049/ip-i-1.1988.0002

出版商:IEE    

年代:1988

数据来源: IET

摘要:

The paper discusses the computation of the large signal admittance and power in Read and abrupt junction structures based on the approximate closed form solution and considering the basic device structure parameters. The results have been compared with the simulation results on the more realistic Read model and found satisfactory throughout a fairly large RF voltage range. The applicability of the analysis for optimum device design is as good as the simulation, with the advantages of lower cost and greater simplicity in terms of the computer program involved.

DOI:10.1049/ip-i-1.1988.0003

出版商:IEE    

年代:1988

数据来源: IET

摘要:

An AC measurement technique is applied to NMOS and PMOS devices fabricated using a 1.25 μm CMOS process. The parasitic resistance and mobility degradation coefficients have been extracted for temperatures between 25 K and 300 K. The NMOS parasitic resistance stays flat with temperature while the PMOS resistance rises sharply below 200 K, probably due to the light source/drain diffusion doping. The mobility reduction parameterθ, shows a clear 1/T behaviour between 100 K and room temperature, withθapproaching unity for the PMOS devices. This may have serious implications for the performance of highly scaled devices which operate at high transverse electrical fields.

DOI:10.1049/ip-i-1.1988.0004

出版商:IEE    

年代:1988

数据来源: IET

摘要:

The influence of a preoxidation cleaning procedure including an (HF + ethanol) step is investigated. It is shown that such a treatment gives a better thickness uniformity and improves the breakdown strength of silica layers.

DOI:10.1049/ip-i-1.1988.0005

出版商:IEE    

年代:1988

数据来源: IET