VLSI and WSI associative string processors for structured data processing
作者:
R.M.Lea,
期刊:
IEE Proceedings E (Computers and Digital Techniques)
(IET Available online 1986)
卷期:
Volume 133,
issue 3
页码: 153-162
年代: 1986
DOI:10.1049/ip-e.1986.0020
出版商: IEE
数据来源: IET
摘要:
A novel fine-grain parallel-processing microelectronic architecture is proposed as a cost-effective building-block for fifth-generation computer systems. Based on a fully programmable associative string processing computational structure, the architecture provides particularly flexible support and manipulation of abstract data structures over a wide range of information processing tasks. Moreover, the architecture is well suited to the technological constraints of VLSI chip and, especially, WSI device fabrication. The paper describes the ASP (associative string processor) architecture and its instruction set. The style of associative string processing is introduced with three algorithms, illustrating both relational and arithmetic operations. Current projects leading to VLSI ASP chips and WSI ASP devices are discussed and ‘ball-park’ performance figures are given.
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