The paper reviews the reasons for and the problems of synchronising the processors of a faulttolerant system and of matching the data in them. It is known that exact solutions require at least (3t+ 1) channels fort-fault-tolerance, but that more economical solutions with only (2t+ 1) channels are feasible when assumptions are made which ensure consistent data in the fault-free processors. The assumptions and the efficiencies of previous algorithms are discussed in the light of overall reliability targets, and the relevance of ‘malicious’ faults and interactive consistency are highlighted. New minimum-hardware solutions are introduced which are particularly suited to microprocessor applications.