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Technical memorandum. Systolic array implementation of a decimator and an interpolator

 

作者: T.S.Okullo-Oballa,   H.K.Kwan,  

 

期刊: IEE Proceedings E (Computers and Digital Techniques)  （IET Available online 1988）
卷期: Volume 135, issue 1  

页码: 70-72

 

年代: 1988

 

DOI:10.1049/ip-e.1988.0010

 

出版商: IEE

 

数据来源: IET

 

摘要:

Two systolic arrays for the VLSI implementation of the decimation and interpolating structures advanced by Valenzuela and Constantinides are presented. Each of the resultant arrays consists of basic cells characterised by nearest neighbour interconnections and high throughput rate.

 

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