Testability and self-test in NMOS and CMOS VLSI signal processors
作者:
A.F.Murray,
P.B.Denyer,
期刊:
IEE Proceedings G (Electronic Circuits and Systems)
(IET Available online 1985)
卷期:
Volume 132,
issue 3
页码: 93-104
年代: 1985
DOI:10.1049/ip-g-1.1985.0021
出版商: IEE
数据来源: IET
摘要:
The paper presents a system of random pattern/signature analysis self-test in NMOS bit-serial signal processing chips, designed by a silicon compiler. Fault coverage is very high, and is determined without full fault simulation. A trial design shows that the cost in silicon, power, complexity and design difficulty is extremely low. A hierarchical system test can be performed, thus permitting fault tolerance. A dynamic CMOS design style supersedes that of the NMOS bit-serial cells. The problem of generating tests for stuck-open faults is removed. This is proved analytically and fault simulation results are presented.
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