AbstractHigh integration density and high‐speed operation are obtainable by miniaturization of bipolar LSI devices. In modern bipolar integrated transistors, an undesired current flows into the substrate due to the parasitic sub‐PNP transistor. For example, for Bi‐CMOS circuits, this substrate current can be the main cause of reduction in the supply voltage.This paper proposes merged models for the NPN and lateral PNP transistors which include the substrate current due to the parasitic sub‐PNP transistor. The extraction of model parameters for the calculation of substrate current is also described. By the application of these models to the simulation of NPN transistor for Bi‐CMOS memory and lateral PNP transistor of linear process, good accuracy of dc saturation and substrate current characteristics can be obtained. Its application to the simulation of decoder/memory cell of Bi‐CMOS memory is d