High-speed bus arbiter for multiprocessors
作者:
A.B.Kovaleski,
期刊:
IEE Proceedings E (Computers and Digital Techniques)
(IET Available online 1983)
卷期:
Volume 130,
issue 2
页码: 49-56
年代: 1983
DOI:10.1049/ip-e.1983.0013
出版商: IEE
数据来源: IET
摘要:
Shared-bus interconnection schemes normally suffer from insufficient capacity. Increasing their bandwidth reduces the problem but makes bus arbitration somewhat difficult. This paper presents a fair bus-arbiter design, its implementation and simulation results. Although the techniques originated from the particular constraints of the architecture considered, it is generally applicable to high-speed arbitration problems and has a low hardware cost.
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