As we move into the VLSI era, many investigations have been performed on enhancement-mode MOS transistors, and the results have often been used for the depletion-mode device. In order to evaluate the differences from the usual enhancement-mode device, and to understand its own behaviour, we have first made an accurate modelling of a large and wide buried-channel device, assuming a step doping profile. Then, an attempt was made to model the narrow- and short-channel effects, based on regional approaches. The model relies on the assumption that the narrow-channel effect is due to the increase in bulk charge due to the parasiticp+-n+(field implant-buried layer) diode. For the short-channel effect, our investigations led us to assume that the effective implanted dose is increased by the diffusion of majority carriers from source and drain, which charge is shared between source, drain, bulk and gate. The excess of positive charge controlled by the gate (instead of the lack of negative charge that characterises the short-channel effect of an enhancement-mode MOSFET) can be evaluated with a geometrical approach, by making a double trapezoidal partioning. The surface and buried-channel conductions, as well as the non-pinch-off current are then taken into account to establish the current equations:IDtot= IDsurf+ IDB.C+ IDn.pinch-off. whereIDsurforIDB.C=f{VDS, VGS, VBSVT(L, W, VBS, VDS)}. The three kinds of current can exist separately or together, thus defining different equations for the total current flowing from source to drain. Comparison with experiments shows a good agreement, and, furthermore, the extracted parameters are very well related to technological parameters. Short and narrow channel transistors, down to micron dimensions, are fairly well described by the model, and one single set of parameters. In conclusion, the depletion-mode transistor appears to be more sensitive to geometry than the enhancement-mode device because of its special structure, and so we need a peculiar model and parameters for this device to get an efficient simulation of circuits fabricated in HMOS technology, where depletion-mode transistors are extensively used as active loads.