Behavioural description and VLSI verification
作者:
G.J.Milne,
期刊:
IEE Proceedings E (Computers and Digital Techniques)
(IET Available online 1986)
卷期:
Volume 133,
issue 3
页码: 127-137
年代: 1986
DOI:10.1049/ip-e.1986.0017
出版商: IEE
数据来源: IET
摘要:
Validation of VLSI design correctness by formal proof is an alternative to the traditional approach which utilises simulation. Formal verification requires the description of the behavior of designs and design specifications, resulting in the development of behavioural description languages. These differ from inherently structural hardware description languages (HDLs) in that they not only allow behaviour and structure to be described, they also support formal behavioural analysis using mathematical techniques. Necessary features of a behavioural description language are presented and the application of this language to VLSI description, design and verification is illustrated.
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