An automatic channel router for integrated circuits is presented. It operates, as is commonplace with this kind of router, in two stages: the global router is based on a relative placement of subcell instances and it is executed only once during the layout generation process of a specific cell. The detailed router, however, operates in an iterative mode. Initially, the subcell instances are placed as close as possible, in accordance with the given relative placement specification. This absolute placement is then gradually expanded until the channels become properly dimensioned so as to hold all the connections allocated to them at the preceding global routing stage. The expansion is driven by feedback information at the end of each iteration about the failures to route connections in the currently available space.