Aid to hierarchial and structured logic design using temporal logic and Prolog
作者:
S.Fujita,
S.Kono,
H.Tanaka,
T.Moto-Oka,
期刊:
IEE Proceedings E (Computers and Digital Techniques)
(IET Available online 1986)
卷期:
Volume 133,
issue 5
页码: 283-294
年代: 1986
DOI:10.1049/ip-e.1986.0035
出版商: IEE
数据来源: IET
摘要:
The paper describes a study of an aid for hardware logic design using temporal logic, called linear time temporal logic (LTTL), and Prolog. A review of specification techniques for synchronisation parts using LTTL is given. A temporal logic programming language called Tokio, which is based on LTTL and includes interval variables, is presented. As parallelisms are tedious to describe sequentially in LTTL, the notion of interval variables which express a finite number of successive times is introduced.
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