A SAW piezoelectric delay line has been integrated with a silicon charge‐coupled shift register device (CCD) across a 300‐nm gap to produce a fast‐in slow‐out buffer memory. A prototype with an input bandwidth of 40 MHz centered around 107 MHz, an input signal duration time of 3.5 &mgr;s, and an output clock rate of 100 kHz has been fabricated and tested. The basic configuration of this SAW/CCD consists of a lithium niobate (LiNbO3) delay line, in close proximity to an array of 300 sampling fingers connected to a 300‐stage buried‐channel CCD on ap‐type silicon susbtrate. The output of the CCD retains both amplitude and phase of the input signal.