VLSI circuits currently being designed are so complex that it is now extremely difficult to test them adequately to determine whether or not they have been processed correctly. Design for testability (DFT) techniques are often used in an attempt to ease this problem by identifying and redesigning potentially ‘difficult-to-test’ parts of the circuits. The ‘testability’ of the circuit is usually evaluated in terms of the stuck-at fault model. However, there have been growing doubts over the ability of this model to cover certain common faults that can occur in MOS processing (at present, the dominant VLSI technology). The paper describes software simulations of faults in simple NMOS logic circuits showing that not all fault effects in NMOS circuits are modellable as ‘stuck’ nodes. An improved fault model which would better reflect MOS fault effects has yet to be defined. Until such an improved model is available, DFT rules for MOS circuits are best regarded as provisional. We therefore conclude with a discussion ofad hoc‘physical design for testability’ techniques that exploit current understanding of the relation between MOS faults and their fault effects.